25 Mbps discrete logic transceiver for learning purposes
Introduction I am about to build a full PHY (physical, duh) layer for data transmission that simulates the multi-Gbps transceiver circuits usually seen in high-end FPGAs and ASICs. The reason I’m doing that is to get a closer understanding of the inner architecture of these advanced circuits, so ubiquitous in modern communication systems. To really … Continue reading 25 Mbps discrete logic transceiver for learning purposes
HELENTRONICA 