25 Mbps discrete logic transceiver: Building a 25 MHz PLL with 74HC4046
Introduction In the receiver portion of my “25 Mbps discrete logic transceiver” project, I will eventually need a functional phase-locked loop (PLL) for one reason or another, but certainly for the clock data recovery circuit (CDR). Browsing the suitable components, that is, 5V CMOS, able to work with 25 MHz, not being super clunky and … Continue reading 25 Mbps discrete logic transceiver: Building a 25 MHz PLL with 74HC4046
HELENTRONICA 