Category: transciever

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25 Mbps discrete logic transceiver: Building a 25 MHz PLL with 74HC4046

Introduction In the receiver portion of my “25 Mbps discrete logic transceiver” project, I will eventually need a functional phase-locked loop (PLL) for one reason or another, but certainly for the clock data recovery circuit (CDR). Browsing the suitable components, that is, 5V CMOS, able to work with 25 MHz, not being super clunky and … Continue reading 25 Mbps discrete logic transceiver: Building a 25 MHz PLL with 74HC4046

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25 Mbps discrete logic transceiver for learning purposes

Introduction I am about to build a full PHY (physical, duh) layer for data transmission that simulates the multi-Gbps transceiver circuits usually seen in high-end FPGAs and ASICs. The reason I’m doing that is to get a closer understanding of the inner architecture of these advanced circuits, so ubiquitous in modern communication systems. To really … Continue reading 25 Mbps discrete logic transceiver for learning purposes